搜索资源列表
uart_rx
- actel A3P250 fpga用VERILOG HDL语言实现串口功能的源代码
testuart2
- verilog语言，硬件调试，用于actel刚推出的fusion系列芯片的接口调试
UART_send
- Verilog HDL 串口发送程序，在ACTEL Fusion FPGA上实验成功 ，和大家一起分享！^_^
UART_rec
- verilog 串口接收程序，在ACTEL Fusion FPGA上实验成功 和大家一起分享！^_^
UART.rar
- 主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程，开发环境：LiberoIDE 8.5,The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5
Libra_ps2key_lcd.rar
- 用Verilog语言实现的PS2小键盘输入和1602 LCD显示的功能。无需修改，已经调试通过了。直接可以当成一个模块用于FPGA/CPLD系统开发过程。 这个代码是我在Libra环境下开发Actel FPGA时写的。,Verilog language using the PS2 keyboard and a small 1602 LCD display features. No changes have been adopted debugging. Directly as a module
ACTEL-FPGA-1602(Verilog)
- 1602液晶显示程序，用verilog写的！-1602 LCD program, written using verilog!
my_and
- 此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development
hdlcode_ug
- Verilog HDL Coding Guidelines - ACTEL -Verilog HDL Coding Guidelines- ACTEL
hdl
- ACTEL串口收发 Verilog语言描述-ACTEL serial port transceiver
hdl
- ACTEL FPGA 1602显示，verilog描述-ACTEL FPGA 1602 show, verilog descr iption
hdl
- ACTEL FPGA 交通灯，Verilog描述-ACTEL FPGA traffic lights, Verilog descr iption
RTC
- actel fpga开发板fusion startkit实验例程，包含完整工程文件几verilog HDL 源码-actel fpga development board fusion startkit test routines, including the complete works of several verilog HDL source file
D_latch
- actel fpga Verilog D锁存器-actel fpga Verilog D latch
my_RAM
- pdf actel fpga verilog ram读写-pdf actel fpga verilog ram read and write
AES_test
- verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
FlashLock_test
- pdf actel fpga verilog FLASH读写-pdf actel fpga verilog FLASH write
三角函数的Verilog HDL语言实现
- 以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, rea
UartRecv
- 利用FPGA实现简单的串口接收驱动程序，actel。(Using FPGA to implement a simple serial port receiver driver, Actel)
Actel8051Core
- Actel 8051 Verilog core